A. Field of the Invention
The present invention relates generally to semiconductor fabrication techniques and, more particularly, to a method for fabricating a small contact area between an upper and lower electrode for use in phase changeable memory devices such as, for example, chalcogenide memory cells.
B. Description of the Prior Art
The use of electrically writable and erasable phase change materials, i.e., materials that can be electrically switched between generally amorphous and generally crystalline states or between different resistive states while in crystalline form, for electronic memory applications is well known in the art. The use of phase change materials is disclosed, for example, in U.S. Pat. No. 5,296,716, in the names of Ovshinsky et al., the disclosure of which is incorporated herein by reference. U.S. Pat. No. 5,296,716 is believed to indicate generally the state of the art, and to contain a discussion of the current theory of operation of chalcogenide materials.
Generally, as disclosed in the Ovshinsky patent, such phase change materials can be electrically switched between a first structural state where the material is generally amorphous and a second structural state where the material has a generally crystalline local order. The material may also be electrically switched between different detectable states of local order across the entire spectrum between the completely amorphous and the completely crystalline states. That is, the switching of such materials is not required to take place between completely amorphous and completely crystalline states, but rather, the material can be switched in incremental steps reflecting changes of local order to provide a "gray scale" represented by a multiplicity of conditions of local order spanning the spectrum from the completely amorphous state to the completely crystalline state.
Chalcogenide material exhibits different electrical characteristics depending upon its state. For example, in its amorphous state the material exhibits lower electrical conductivity than it does in its crystalline state. The operation of chalcogenide memory cells requires that a region of the chalcogenide memory material, called the chalcogenide active region, be subjected to a current pulse typically with a current density between 10.sup.5 and 10.sup.7 amperes/cm.sup.2, to change the crystalline state of the chalcogenide material within the active region contained within a small pore. This current density may be accomplished by first creating a small opening in a dielectric material that is itself deposited onto a lower electrode material. A second dielectric layer, typically of silicon nitride, is then deposited onto the dielectric layer into the opening. The second dielectric layer is typically about 40 Angstroms thick. The chalcogenide material is then deposited over the second dielectric and into the opening. An upper electrode material is then deposited over the chalcogenide material. Carbon is commonly used as the electrode material, although other materials have also been used, for example, molybdenum and titanium nitride. A conductive path is then provided from the chalcogenide material to the lower electrode material by forming a pore in the second dielectric layer by a well-known firing process.
Firing involves passing an initial high current pulse through the structure that passes through the chalcogenide material and then provides dielectric breakdown of the second dielectric layer, thereby providing a conductive path via the pore created through the memory cell. Electrically firing the thin nitride layer is not desirable for a high density memory product due to the high current required and the large amount of testing time required for the firing.
The active regions of the chalcogenide memory cells within the pores are believed to change crystalline structure in response to applied voltage pulses of a wide range of magnitudes and pulse durations. These changes in crystalline structure alter the bulk resistance of the chalcogenide active region. The wide dynamic range of these devices, the linearity of their response, and lack of hysteresis provide these memory cells with multiple bit storage capabilities.
Factors such as pore dimensions (i.e., diameter, thickness and volume), chalcogenide composition, signal pulse duration and signal pulse waveform shape have an effect on the magnitude of the dynamic range of resistances, the absolute endpoint resistances of the dynamic range, and the currents required to set the memory cells at these resistances. For example, relatively large pore diameters, e.g., about one micron, will result in higher programming current requirements, while relatively small pore diameters, e.g., about 500 Angstroms, will result in lower programming current requirements. The most important factor in reducing the required programming current is the pore cross sectional area.
The energy input required to adjust the crystalline state of the chalcogenide active region of the memory cell is directly proportional to the dimensions of the minimum lateral dimension of the pore, e.g., smaller pore sizes result in smaller energy input requirements. Conventional chalcogenide memory cell fabrication techniques provide minimum lateral pore dimension, diameter or width of the pore, that is limited by the photolithographic size limit. This results in pore sizes having minimum lateral dimensions down to approximately 0.35 microns. However, further reduction in pore size is desirable to achieve improved current density for writing to the memory cell.